1. Field of the Invention
The invention relates generally to system-level computer memory devices and more specifically to memory modules with almost-good dynamic random access memories.
2. Description of the Prior Art
Dynamic random access memory (DRAM) devices have now advanced beyond storing one million bits of information in a single semiconductor chip. Each bit takes at least one transistor to implement not counting the support circuitry, so the number of things that can be flawed in a single chip during its manufacture can exceed a million. So even an exceedingly good manufacturing fab line will produce thousands of bad parts per millions of parts started. It used to be that bad memories were just thrown away, a total loss. Later, some redundancy was built in to repair the bad bits, but the required die sizes got too large to make repairing every bit practical. It was recognized that DRAM devices that were not perfect, and therefore not suited to computer data storage, could be useful as video or audio memory because an occasional bad bit was not fatal in such applications.
Such "mostly good" DRAM devices can nevertheless be successfully used in computer data storage applications when a second, repair memory is wired in tandem to respond when a faulty bit is being accessed in the mostly-good DRAM. Siu Tsang describes such a memory system in U.S. Pat. No. 4,376,300, issued Mar. 8, 1983. A redundant memory chip is used to store data intended for the defective addresses in the mostly-good memories. A programmable read only memory (PROM) is illustrated as controlling a switch that steers data to either a single redundant memory device or several mostly-good memories. Whole rows addressed by a system address bus in the mostly-good memories are substituted by equivalent whole rows in the redundant memory, even when only one bit in a row of bits is bad. In a one megabit memory, there are a thousand rows and a thousand columns. Each row therefore comprises a thousand bits. Because of this, the embodiments described by Tsang are very wasteful because good memory is substituted along with the bad. The mostly-good memories must all be of the same type, e.g., with the same row and column organization, and have the same access modes. The systems described require that no two mostly-good memories have bad bits in the same row, due to the simple way that the redundant memory is connected directly to receive the address bus alongside the mostly-good memories.
In his FIG. 2, Tsang proposes the use of a content addressable memory (CAM) in front of the redundant memory address inputs. But, such a method is expensive and the throughput of most CAMs is very poor, compared to the access times of the DRAMs of interest. With microprocessor clock speeds now exceeding one hundred megahertz, such access delays are totally unacceptable.